As described in Japanese publication of unexamined patent application, Tokukai, NO. 2001-307495 (Date of Publication: Nov. 2, 2001) and the like, shift registers have been widely used in data line (data signal line) driving circuits and gate line (scanning signal line) driving circuits, for timing in sampling data signals in each data line and for generating a scanning signal for each gate line, and the like.
In a data line driving circuit, a shift register outputs a sampling signal so as to write a video signal into each data line. Meanwhile, in the gate line driving circuit, the shift register outputs a scanning signal so as to sequentially write the video signal supplied to each data line into pixels arrayed in a display section.
The following describes the shift register. As shown in FIG. 11, the shift register includes plural stages of flip-flops that operate in synchronization with clock signals CK and CKB.
The flip-flops shown in FIG. 11 are set-reset type flip-flops (SR flip-flops). For example, an output from an (i+1) th (here, 2≦i+1≦n; i is an integer number) flip-flop Fi+1 is inputted to a reset terminal R of a preceding (i-th) flip-flop Fi as a reset signal.
In general, a flip-flop is a circuit that switches over between two stable states every time a signal is inputted with certain timing, and stays in one of the stable states while no signal is inputted.
Specifically, in the SR flip-flops (hereinafter the flip-flops), for example, an output from an i-th flip-flop Fi is switched to be in a low state when a set signal (that is, a low output (an output signal) from an (i−1) th flip-flop Fi−1) and a low clock signal CK or CKB synchronized with the i-th flip-flop Fi are inputted to the i-th flip-flop Fi. The output from the i-th flip-flop Fi stay in the state even if the set signal inputted becomes non-active.
Thereafter, when the set signal inputted is non-active and, for example, a reset signal from the (i+1) th flip-flop Fi+1 becomes active, the output of the flip-flop Fi transits to a high state. After that, even if the reset signal from the (i+1) th flip-flop Fi+1 becomes non-active, the state is kept until the set signal inputted becomes active.
Then, the (i+1) the flip-flop Fi+1 is set when the output from the flip-flop Fi+1 is in a low state. The output from the flip-flop Fi+1 is switched to the low state in accordance with timings of the clock signals CK and CKB that are synchronized with the (i+1) th flip-flop Fi+1. When a reset signal (an output signal) from an (i+2) th flip-flop Fi+2 becomes active, the output of the (i+1) th flip-flop Fi+1 transits to the high state.
Thereafter, even if the reset signal from the (i+2) th flip-flop Fi+2 becomes non-active, the state is kept until the set signal inputted becomes active.
Thus, a pulse is shifted through the flip-flops in accordance with outputs of set signals S from preceding flip-flops and reset signals R from following flip-flops.
Each output signal from the flip-flops is outputted as the set signal for the following flip-flop thereof, and inputted to the preceding flip-flop thereof as the reset signal for resetting the preceding flip-flop.
Thus, the flip-flops that have outputted signals are reset as the pulse is shifted through the flip-flops.
Then, an output signal from a last-stage flip-flop Fn is inputted to an (n−1) th flip-flop Fn−1 so as to reset the (n−1) th flip-flop Fn−1, and is inputted to the flip-flop Fn so as to reset the flip-flop Fn.
In short, the last-stage flip-flop Fn supplies the output signal to the preceding flip-flop Fn−1 and to itself (the last-stage flip-flop Fn) as reset signals therefor.
Thus, it is necessary to stop (self-reset) operation of the last-stage flip-flop Fn by using the output signal from the last-stage flip-flop Fn itself. Therefore, such operation control of self-reset is necessary.
Liquid crystal image display devices have been widely used recently as display devices for small portable terminals and for mobile phones. Furthermore, because infrastructures for communications have been improved, broadband has become common, thereby increasing amount of information.
For the above reasons, it is strongly desired that display sections of the small portable terminals and the mobile phones have large display capacity so that more information can be displayed in a screen.
If the display capacity becomes large, data clock speed becomes very high. For example, where a frame frequency is 60 Hz, data rate is about 25 MHz for displaying VGAs (video graphics arrays), whilst the data rate is 75 MHz for displaying SXGAs (super extended graphics arrays).
However, if the display capacity becomes large, for example, it is necessary that circuit operation in a circuit part in the image display device be carried out at high speed. In such a case, there is a fear that delay in the circuits may cause malfunctions of the circuits.
For example, where the shift register includes the flip-flops F1 to Fn shown in FIG. 11, there is a case in which the reset signal is not supplied in a right timing, the reset signal being supplied, from the n-th flip-flop Fn, for stopping (resetting) operation of the (n−1) th flip-flop Fn−1. In this case, it is failed to stop the operation of the (n−1) th flip-flop Fn−1.
More specifically, due to capacitance, resistance, and the like of the wires through which the output signal from the n-th flip-flop Fn is inputted to the (n−1) th flip-flop Fn−1 as the reset signal, or because a driving frequency becomes higher, the last-stage (n-th) flip-flop Fn is reset before the (n−1) th flip-flop Fn−1 is reset by the output signal from the flip-flop Fn as the reset signal having enough driving capability.
Because of this, the last-stage flip-flop Fn stops operating before the (n−1) th flip-flop Fn−1 stops operating, whereby the reset signal is not inputted to the (n−1) th flip-flop Fn−1. This leads to, as shown in FIG. 12, failure of resetting the (n−1) th flip-flop Fn−1.
In other words, because the (n−1) th flip-flop Fn−1 keeps operating without being reset, a desired sampling waveform cannot be obtained at a last data line (that receives a last data signal in one horizontal period) in the data driving circuit.
Moreover, in the gate (scanning) driving circuit, a desired scanning signal for sequentially writing video signals in the pixels arrayed at the display section cannot be obtained in a last gate line (that receives a last scanning signal in one frame period).
Furthermore, in case of a shift register capable of performing scanning in two directions, last-stage flip-flops in each scanning direction (those flip-flops that reset themselves and the preceding flip-flops thereof) are at both ends of the shift register.
In such an arrangement, floated are set terminals S and reset terminals R of the flip-flops that contribute only to scanning in one of the directions (a leftmost flip-flop in case of a scanning in a rightward direction and a rightmost flip-flop in case of a scanning in a leftward direction).
When the input terminals are floated, potential of the input terminals become unstable, and there is a fear that the flip-flops are set at certain moment and start operating.
In this case the flip-flops that are set are instantly reset by their own resetting function. However, the flip-flops thus reset are again floated. Thus, the flip-flops that are set again. The flip-flops keep always operating because the flip-flops are set and then reset again and again.